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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. november 2007 rev 0.2 1/22 1 m36l0t7050t2 M36L0T7050B2 128 mbit (multiple bank, mult i-level, burst) flash memory and 32 mbit (2mb x16) psram, multi-chip package feature summary multi-chip package ? 1 die of 128 mbit (8mb x16, multiple bank, multi-level, burst) flash memory ? 1 die of 32 mbit (2mb x16) pseudo sram supply voltage ?v ddf = 1.7 to 1.95v ?v ccp = v ddq = 2.7 to 3.1v ?v ppf = 9v for fast program electronic signature ? manufacturer code: 20h ? device code (top flash configuration) m36l0t7050t2: 88c4h ? device code (bottom flash configuration) M36L0T7050B2: 88c5h ecopack? packages available flash memory synchronous / asynchronous read ? synchronous burst read mode: 52mhz ? random access: 85ns synchronous burst read suspend programming time ? 2.5s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 8 mbit banks ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp for block lock-down ? absolute write protection with v pp = v ss security ? 64 bit unique device number ? 2112 bit user programmable otp cells common flash interface (cfi) 100,000 program/erase cycles per block psram access time: 65ns 8-word page access capability: 18ns low standby current: 100a deep power down current: 10a compatible with standard lpsram power-down modes ? deep power-down ? 4 mbit partial array refresh ? 8 mbit partial array refresh tfbga88 (zaq) 8 x 10mm fbga www.numonyx.com
contents m36l0t7050t2, M36L0T7050B2 2/22 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 data input/output (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 flash chip enable (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 flash output enable (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 flash write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 flash write protect (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 flash reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 flash latch enable (l f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 flash clock (k f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 flash wait (wait f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 psram chip enable input (e1 p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 psram chip enable input (e2 p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 psram write enable (w p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 psram output enable (g p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 psram upper byte enable (ub p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 psram lower byte enable (lb p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.17 v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.18 v ccp supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.19 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.20 v ppf program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
m36l0t7050t2, M36L0T7050B2 contents 3/22 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of tables m36l0t7050t2, M36L0T7050B2 4/22 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. device capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, package data . . . . . . 19 table 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m36l0t7050t2, M36L0T7050B2 list of figures 5/22 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, bottom view outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
summary description m36l0t7050t2, M36L0T7050B2 6/22 1 summary description the m36l0t7050t2 and M36L0T7050B2 combine two memory devices in a multi-chip package: a 128-mbit, multiple bank, multi-level, burst, flash memory, the m58lt128ht or m58lt128hb a 32-mbit pseudosram, the m69kw048bd. the purpose of this document is to describe how the two memory components operate with respect to each other. it should be read in conjunction with the m58lt128htb and m69kw048bd datasheets, where all specifications required to operate the flash memory and psram components are fully detailed. these datasheets are available from your local numonyx distributor. recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. the devices are supplied with all the bits erased (set to ?1?). figure 1. logic diagram ai12878 23 a0-a22 dq0-dq15 m36l0t7050t2 M36L0T7050B2 g f 16 w f rp f wp f e1 p g p w p ub p lb p v ss v ddf v ppf v ccp wait f l f k f v ddq e f e2 p
m36l0t7050t2, M36L0T7050B2 summary description 7/22 table 1. signal names a0-a22 (1) 1. a22-a21 are not connected to the psram component. address inputs dq0-dq15 common data input/output v ddf power supply for flash memory v ddq flash memory power supply for i/o buffers v ppf flash optional supply voltage for fast program and erase v ss ground v ccp psram power supply nc not connected internally du do not use as internally connected flash memory signals l f latch enable input e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input k f burst clock wait f wait data in burst mode psram signals e1 p chip enable input g p output enable input w p write enable input e2 p power-down input ub p upper byte enable input lb p lower byte enable input
summary description m36l0t7050t2, M36L0T7050B2 8/22 figure 2. tfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b a21 k f a4 a11 d e f du du w f v ss a19 a18 a22 a5 a12 v ss nc lb p a9 a3 a13 v ppf nc a17 a10 a20 a2 a15 l f wp f nc a7 a14 a8 a1 a16 rp f ub p a6 wait f dq13 a0 dq5 dq10 dq2 dq8 dq7 dq14 g p dq12 dq3 dq1 dq0 dq15 dq6 dq4 dq11 dq9 g f v ddq e f e2 p v ccp v ss v ss v ss v ss v ss v ddf v ddq v ss du du du du du du a g h j k ai08735b l m v ddf nc w p e p nc nc du du nc nc nc nc v ddq
m36l0t7050t2, M36L0T7050B2 signal descriptions 9/22 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a22) addresses a0-a20 are common inputs for the flash memory and the psram components. the other lines (a21-a22) are inputs for the flash memory component only. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller in the flash memory, and they select the cells to be accessed in the psram. 2.2 data input/output (dq0-dq15) in the flash memory, the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. in the psram dq0-dq7 and/or dq8-dq15 carry the data to or from the upper and/or lower part(s) of the selected address during a write or read operation, when upper byte enable (ub p ) and/or lower byte enable (lb p ) is/are driven low. 2.3 flash chip enable (e f ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , and reset is high, v ih , the device is in active mode. when chip enable is at v ih the flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. it is not allowed to set e f at v il, e1 p at v il and e2 p at v ih at the same time. 2.4 flash output enable (g f ) the output enable input controls data output during flash memory bus read operations. 2.5 flash write enable (w f ) the write enable controls the bus write operation of the flash memories? command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first.
signal descriptions m36l0t7050t2, M36L0T7050B2 10/22 2.6 flash write protect (wp f ) write protect is an input that gives an additional hardware protection for each block. when write protect is low, v il , lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at high, v ih , lock-down is disabled and the locked-down blocks can be locked or unlocked. (see the lock status table in the m58lt128htb datasheet). 2.7 flash reset (rp f ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to m58lt128htb datasheet for the value of i dd2 . after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to m58lt128htb datasheet). 2.8 flash latch enable (l f ) latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is low, v il , and it is inhibited when latch enable is high, v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. 2.9 flash clock (k f ) the clock input synchronizes the flash memory to the microcontroller during synchronous read operations; the address is latched on a cl ock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is don't care during asynchronous read and in write operations. 2.10 flash wait (wait f ) wait is a flash output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when flash chip enable is at v ih or flash reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. the wait f signal is not gated by output enable. 2.11 psram chip enable input (e1 p ) when asserted (low), the chip enable, e1 p , activates the memory state machine, address buffers and decoders, allowing read and write operations to be performed. when de- asserted (high), all other pins are ignored, and the device is put, automatically, in low-power standby mode. it is not allowed to set e f at v il, e1 p at v il and e2 p at v ih at the same time.
m36l0t7050t2, M36L0T7050B2 signal descriptions 11/22 2.12 psram chip enable input (e2 p ) the chip enable, e2 p , puts the device in deep power-down mode when it is driven low. this is the lowest power mode. 2.13 psram write enable (w p ) the write enable, w p , controls the bus write operation of the memory. 2.14 psram output enable (g p ) the output enable, g p , provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. 2.15 psram upper byte enable (ub p ) the upper byte enable, ub p , gates the data on the upper byte data inputs/outputs (dq8- dq15) to or from the upper part of the selected address during a write or read operation. 2.16 psram lower byte enable (lb p ) the lower byte enable, lb p , gates the data on the lower byte data inputs/outputs (dq0- dq7) to or from the lower part of the selected address during a write or read operation. 2.17 v ddf supply voltage v ddf provides the power supply to the internal cores of the flash memory component. it is the main power supply for all flash operations (read, program and erase). 2.18 v ccp supply voltage the v ccp supply voltage supplies the power for all operations (read or write) and for driving the refresh logic, even when the device is not being accessed. 2.19 v ddq supply voltage v ddq provides the power supply for the flash memory i/o pins. this allows all outputs to be powered independently of the flash memory core power supply, v ddf .
signal descriptions m36l0t7050t2, M36L0T7050B2 12/22 2.20 v ppf program supply voltage v ppf is both a flash control input and a flash power supply pin. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddq ) v ppf is seen as a control input. in this case a voltage lower than v pplkf gives an absolute protection against program or erase, while v ppf > v pp1 enables these functions (see the m58lt128htb datasheet for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pph it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. 2.21 v ss ground v ss is the common ground reference for all voltage measurements in the flash (core and i/o buffers) and psram chips. note: the flash memory device in a system should have their supply voltage (v ddf ) and the program supply voltage v ppf decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance capaci tors should be as close as possible to the package). see figure 5: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v ppf program and erase currents.
m36l0t7050t2, M36L0T7050B2 functional description 13/22 3 functional description the psram and flash memory components have separate power supplies but share the same grounds. they are distinguished by three chip enable inputs: e f for the flash memory and e1 p and e2 p for the psram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is simultaneous read operations in the flash memory and the psram which would result in a data bus contention. therefore it is recommended to put the other device in the high impedance state when reading the selected device. figure 3. functional block diagram ai10965 rp f wp f e1 p e2 p g p w p dq0-dq15 v ddf v ppf a20-a22 16 mbit psram g f w f ub p lb p wait f k f l f v ss 128 mbit flash memory v ccp e f a0-a19 v ddq
functional description m36l0t7050t2, M36L0T7050B2 14/22 table 2. operating modes (1) operation e f g f w f l f rp f wait f (2) e1 p e2 p g p w p lb p ,ub p dq0- dq7 dq8- dq15 flash read v il v il v ih v il (3) v ih psram must be disabled data out flash write v il v ih v il v il (3) v ih data in flash address latch v il xv ih v il v ih data out or hi-z (4) flash output disable v il v ih v ih xv ih hi-z any psram mode is allowed hi-z flash standby v ih xx x v ih hi-z hi-z flash reset x x x x v il hi-z hi-z psram read (5) flash memory must be disabled v il v ih v il v ih v il v ih data out hi-z v il v ih v il v ih v ih v il hi-z data out v il v ih v il v ih v il v il data out psram write (5) v il v ih v ih v il v il v ih data in hi-z v il v ih v ih v il v ih v il hi-z data in v il v ih v ih (6) v il v il v il data in psram output disabled (5) any flash mode is allowed v il v ih v ih v il v ih v ih hi-z v il v ih psram standby (deselected) v ih v ih xx x hi-z psram power- down (7) xv il xx x hi-z 1. x = don't care. 2. wait signal polarity is configured us ing the set configuration register command. see the m58lt128htb datasheet for details. 3. l f can be tied to v ih if the valid address has been previously latched. 4. depends on g f . 5. should not be kept in this logic condition for a period longer than 1s. 6. g p can be v il during the write operation if the following conditions are satisfied: a. write pulse is initiated by e1 p (e1 p controlled write timing), or cycle time of the previous operatio n cycle is satisfied; b. g p stays v il during the entire write cycle. 7. power-down mode can be entered from standby state and all da ta outputs are in high-z. the power-down current and data retention depend on the selection of power-down programming.
m36l0t7050t2, M36L0T7050B2 maximum rating 15/22 4 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?55 125 c v io input or output voltage ?0.5 3.6 v v ddf flash memory core supply voltage ?0.2 2.5 v v ddq , v ccp psram and input/output supply voltages ?0.2 3.6 v v ppf flash program voltage ?0.2 10 v i o output short circuit current ? 100 ma t vppfh time for v ppf at v ppfh 100 hours
dc and ac parameters m36l0t7050t2, M36L0T7050B2 16/22 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 4. operating and ac measurement conditions parameter flash memories psram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v ccp supply voltage ? ? 2.7 3.1 v v ddq supply voltage 2.7 3.1 ? ? v v ppf supply voltage (factory environment) 8.5 9.5 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ? ? v ambient operating temperature ?25 85 ?30 85 c load capacitance (c l )3050pf output circuit resistors (r 1 , r 2 )2222k input rise and fall times 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2
m36l0t7050t2, M36L0T7050B2 dc and ac parameters 17/22 figure 5. ac measurement load circuit please refer to the m58lt128htb and m69kw048bd datasheets for further dc and ac characteristic values and illustrations. table 5. device capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 12 pf c out output capacitance v out = 0v 15 pf ai08364b v ddq c l c l includes jig capacitance r 1 device under test 0.1f v ddq r 2 0.1f v ddf
package mechanical m36l0t7050t2, M36L0T7050B2 18/22 6 package mechanical in order to meet environmental requirements, numonyx offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 6. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, bottom view outline 1. drawing is not to scale. a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
m36l0t7050t2, M36L0T7050B2 package mechanical 19/22 table 6. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, package data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157
part numbering m36l0t7050t2, M36L0T7050B2 20/22 7 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 7. ordering information scheme example: m36 l 0 t 7 0 5 0 t 2 zaq f device type m36 = multi-chip package (flash + ram) flash 1 architecture l = multilevel, multiple bank, burst mode flash 2 architecture 0 = no die operating voltage t = v ddf = 1.7 to 1.95v; v ddq = v ccp = 2.7 to 3.1v flash 1 density 7 = 128 mbit flash 2 density 0 = no die ram 1 density 5 = 32 mbit ram 0 density 0 = no die parameter blocks location t = top boot block flash b = bottom boot block flash product version 2 = 90nm flash technology and multi-leve l design, 85ns speed; 0.13m ram, 65ns speed package zaq = stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch option blank = standard packing t = tape & reel packing e = ecopack? package, standard packing f = ecopack? package, tape and reel packing
m36l0t7050t2, M36L0T7050B2 revision history 21/22 8 revision history table 8. document revision history date revision changes 04-may-2006 01 initial release. 13-nov-2007 02 applied numonyx branding.
m36l0t7050t2, M36L0T7050B2 22/22 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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